No subject

are being achieved through more channels (i.e., replication) and by
migrating from DDR2 to DDR3.  This improves the bandwidth to memory, but
does not improve the latency of the underlying memory cells.  (Ref:
http://en.wikipedia.org/wiki/DDR3_SDRAM).  

Unfortunately, BGP has an annoying tendency to do fairly random access (tree
walks) through large data sets and then perform read-modify-write operations
(e.g., adding a path to an existing route and then performing the best-path
computation), certain operations such as caching and pre-fetching have
limited benefits and latency remains the key concern.

In short, unless there's a significant change in the underlying technology
of the single DRAM cell, things aren't going to change significantly.

Regards,
Tony